The present invention relates to a differential amplifier in which the input common-mode is adjustable.
Differential amplifiers are fundamental building blocks in analog integrated circuit design. The input common-mode voltage of a differential amplifier, defined as the average of the two input signals applied to the differential amplifier, is an important design specification. In DC coupled differential amplifiers, the input common-mode is set by the positive and negative signals applied to the differential amplifier. However, there are a wide variety of analog MOS sample data circuits in which the input signals are capacitively coupled and the input common-mode is set by a separate common-mode circuit.
A commonly used circuit for a differential amplifier 10 is shown in FIG. 1. In differential amplifier 10, input transistors M1 and M2, in combination with tail current source I.sub.REF, form an input differential pair. Devices M3 and M4 form cascoding devices which reduce the input capacitance at the gates of input transistors Ml and M2 in a well-known manner. Diode connected transistors M5 and M6 form a differential load and also set the output common-mode for the differential amplifier 10. The output common-mode voltage for differential amplifier 10 is set at V.sub.DD -.vertline.V.sub.GS .vertline., where V.sub.DD is the power supply voltage and .vertline.V.sub.GS .vertline. is the absolute value of the gate to source voltage of nominally identical devices M5 and M6.
Ideally, a zero differential input to a differential amplifier should produce a zero differential output. However, due to inherent device mismatches, to obtain a zero differential output a non-zero input signal needs to be applied to the inputs. This non-zero input signal is referred to as the input referred offset-voltage of the differential amplifier. In applications where this offset voltage is not tolerable, the offset voltage can be stored on input capacitors C1 and C2 as shown in FIG. 2. Referring to FIG. 2, before differential amplifier 10 begins amplification, switches S1 and S2 are closed and the inputs V.sub.IP and V.sub.IM are set at their common-mode voltage V.sub.CM. Nodes V1 and V2 charge to a common-mode voltage set by the output of differential amplifier 10. In an offset-free differential amplifier, the voltages at nodes V1 and V2 are substantially equal to the output common-mode voltage of the differential amplifier. However, in the presence of the amplifier offset, the difference between the voltages on nodes V1 and V2 is substantially equal to the amplifier offset. This mode, where the offset and input common-mode of the amplifier and the reference common mode of the input signal are acquired and/or set, is commonly referred to as the "auto-zero" or "offset acquisition" mode.
Once the switches S1 and S2 are opened, differential amplifier 10 is in the amplification mode. In this mode, the offset voltage (which is stored on capacitors C1 and C2) is added to the inputs before they are presented to differential amplifier 10. The result is offset-free amplification. However, because of the capacitive coupling, the input common-mode of differential amplifier 10 is established by differential amplifier 10 itself.
For the differential amplifier circuitry shown in FIGS. 1 and 2, the output common-mode voltage is given by V.sub.DD -.vertline.V.sub.GS .vertline., where .vertline.V.sub.GS .vertline. is the absolute value of the gate-to-source voltage of P-channel transistors M5 and M6. Thus, when the prior art differential amplifier 10 is used in the "auto-zero" mode, nodes V1 and V2 are charged to the value of V.sub.DD -.vertline.V.sub.GS .vertline.. When switches S1 and S2 are opened, the input common-mode of amplifier 10, and thus the gate voltages of transistors M1 and M2, are also set at V.sub.DD -.vertline.V.sub.GS .vertline.. In addition, drain voltages of transistors M1 and M2 are below their gate voltage by an amount equal to the drain-source voltage of devices M3 and M4. To achieve the highest gain-bandwidth product (GBW) for differential amplifier 10, transistors M1 and M2 need to be biased to operate deep in their saturation region. Although saturation can be achieved by keeping the drain voltages of transistors M1 and M2 no lower than a predetermined threshold voltage below their gate voltages, generally, the farther away the drain voltage is set from this threshold limit, the better the gain-bandwidth of amplifier 10 will be. This is especially true when short-channel transistors are used for M1 and M2 (as is often the case for high speed applications), since for short-channel devices the boundary between the triode region of operation and the saturation region of operation is not clearly defined. For these devices a substantial improvement in the transconductance results if the drain voltage is kept further away from the gate voltage.
With the auto-zero technique described above, even in the best case, where cascoding devices M3 and M4 are removed, the drain voltages of transistors M1 and M2 can only equal their gate voltages. The addition of cascoding devices M3 and M4 moves the drain voltages of transistors M1 and M2 below their gate voltages, and further brings transistors M1 and M2 closer to leaving the saturation region. In addition, with the prior art differential amplifier, since the gates of transistors M1 and M2 are biased close to V.sub.DD, the output voltage swing of the differential amplifier 10 is also limited.